The present invention relates to a semiconductor device process, and more specifically, to a method to form a MOSFET with buried contacts and air-gap gate structure.
Recently, the rapid progression of the microelectronic technology demands devices with high speed and capable of operating at a lower voltage to lessen power consumption, as well as to reduce the cost per unit chip. Generally, the method to approach such purpose is to scale the device dimension down. For example, for a CMOS device, as it is scaling to 0.1 xcexcm and operating at 1V range, is known to have the speed enhancement of about 3X performance than the 0.35 xcexcm device operates at 3.3V. However, in short-channel MOSFETs, the stringent issues such as hot carrier effects, punchthrough effects, parasitic resistance, etc., are required to be overcome.
In addition, the parasitic capacitancexe2x80x94the gate fringe capacitor (CFR), around the gate electrode of a MOSFET and the junction capacitance (CJ)-are difficult to reduce. The larger values of the parasitic capacitance give longer RC delay time.
Hence, for realizing high speed and low-power ULSI, minimizing parasitic capacitance is demanded. The COV, the capacitance between source/drain and the gate, and CJ can be reduced by adjusting the sidewall thickness, and by self-aligned counter well doping, or by implanting a channel impurity locally around the gate electrode, as is stated in the paper by M. Togo, et al., titled xe2x80x9cA Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETsxe2x80x9d, Symp. On VLSI Tech. Dig., p. 38 (1996). Besides, Togo et al. also proposed that the transistor with gate-side air-gap structure (GAS) could be used to minimize the CFR. The GAS in which a 5-nm-wide air gap formed next to the gate is found to reduce the fringe capacitance by half. Hence the gate delay time is reduced by 4.8 psec at fan out=1 and 16 psec at fan out=3 in a 0.25 xcexcm CMOS, and the power consumption is lowered compared to a conventional structure. In addition, the GAS structure can not be found to degrade electrical characteristics or reliability, as is depicted in the paper.
The fabrication of the GAS structure as proposed by Togo is shown in FIGS. 1(a)-(d), and will be restated as the following: After the gate is etched, a 20 nm wide Si3N4 sidewall is fabricated (FIG. 1(a)). Next, a 50 nm thickness SiO2 is formed, and is followed by etching back (FIG. 1(b)). After that, the Si3N4 sidewall is removed by a wet etching to form the air gaps (FIG. 1(c)), and 50 nm thick SiO2 layer is then deposited to form the air-gap cap and is etched back (FIG. 1(d)).
The method comprises the following steps: First, a silicon substrate having trench isolations is provided so that an active region is defined. After a pad oxide layer and a nitride layer are sequentially formed on the silicon substrate, a gate region is defined by patterning the nitride layer and the pad oxide layer. For forming the buried contacts, a polysilicon layer is formed on all areas. Subsequently, a CVD oxide layer is then deposited on the polysilicon layer followed by etching back using the nitride layer in the gate region as an etch stopping layer. After the nitride layer in the gate region is removed using hot H3PO4, thereby, a gate hollow region results. After that, the nitride spacer formation on the sidewalls of the gate hollow region is performed. For improving the electrical properties of the gate oxide, the pad oxide layer in the gate hollow region is removed and substituted by regrowing a nitrogen-rich gate oxide. Thereafter, an xcex1-Si layer is deposited on all areas and refills in the gate hollow region, a planarization process using the CVD oxide layer as an etch-stopping layer then follows. Subsequently, the CVD oxide layer is removed using the polysilicon layer as an etch-stopping layer. A low energy, high dose S/D/G implant is then performed. After removing the nitride spacers, another low energy medium dose is implanted into all areas so as to form extended S/D regions beneath the resulting dual-recessed spaces, which is previously occupied by the nitride spacers. Subsequently, another CVD oxide layer is deposited on all areas and sealed the dual-recessed spaces to form air gaps. Finally, a high temperature thermal anneal is performed so as to form source/drain junctions and the extended source/drain junctions by driving the conductive impurities into the silicon substrate. Concurrently, the remnant polysilicon layer serves as the buried contact.